About the role
As a Verification Engineer at IMC, you will be part of the R&D team. You’ll have the opportunity to work on novel solutions to accelerate trading decisions to the technological limit. In addition, you’ll work on forward looking solutions that anticipate future requirements.
Your Core Responsibilities: Work in a small and globally distributed team that takes responsibility for the complete solution Collaborate closely with RTL and SW team to validate complex systems Automate verification flow for fast turn-around time to enable rapid development Use a variety available tools and methods to drive for successful end results Your Skills and Experience: Bachelors in Electrical Engineering, Computer Engineering, or related technical field 3+ years of experience verifying complex hardware designs using UVM Experience working with industry standard 3rd party EDA
tools Experience with regression test automation and tracking Ability to develop system and block level testbenches Understanding of metrics based verification, tracking and reporting coverage to drive to closure Experience in SystemVerilog/Verilog, and C++ Experience with scripting languages Ability to work in a Linux environment The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance.
Please visit Benefits - US | IMC Trading for more comprehensive information. Salary Range $175,000 - $225,000 USD About Us IMC is a research-driven trading firm where quantitative modeling, machine learning, and engineering shape how modern markets are traded. A stabilizing force in markets since 1989, we provide liquidity across trading venues, delivering the best outcome in value and risk management to investors. Using our own technology and capital, we build proprietary systems and algorithms that operate across global markets.
Our researchers, traders, and engineers work as a collective, combining rapid experimentation, advanced infrastructure, and real-time feedback to turn insight into execution and execution into advantage.
Minimum requirements
- Bachelor’s in Electrical/Computer Engineering or related field with 3+ years verifying complex hardware using UVM
- Proficient in SystemVerilog/Verilog, C++, scripting languages, and Linux environment
- Experience with 3rd party EDA tools, regression test automation, and metrics-based verification coverage tracking
This listing was parsed by AI and may not be complete. Check the official posting on IMC's site for the most accurate information.